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Freescale Semiconductor /MK12D5 /FMC /PFAPR

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Interpret as PFAPR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)M0AP 0 (00)M1AP 0 (00)M2AP 0 (00)M3AP 0 (00)M4AP 0 (00)M5AP 0 (00)M6AP 0 (00)M7AP 0 (0)M0PFD 0 (0)M1PFD 0 (0)M2PFD 0 (0)M3PFD 0 (0)M4PFD 0 (0)M5PFD 0 (0)M6PFD 0 (0)M7PFD

M5AP=00, M1PFD=0, M7AP=00, M3PFD=0, M0AP=00, M2AP=00, M2PFD=0, M7PFD=0, M6PFD=0, M4PFD=0, M4AP=00, M3AP=00, M5PFD=0, M1AP=00, M0PFD=0, M6AP=00

Description

Flash Access Protection Register

Fields

M0AP

Master 0 Access Protection

0 (00): No access may be performed by this master

1 (01): Only read accesses may be performed by this master

2 (10): Only write accesses may be performed by this master

3 (11): Both read and write accesses may be performed by this master
M1AP

Master 1 Access Protection

0 (00): No access may be performed by this master

1 (01): Only read accesses may be performed by this master

2 (10): Only write accesses may be performed by this master

3 (11): Both read and write accesses may be performed by this master
M2AP

Master 2 Access Protection

0 (00): No access may be performed by this master

1 (01): Only read accesses may be performed by this master

2 (10): Only write accesses may be performed by this master

3 (11): Both read and write accesses may be performed by this master
M3AP

Master 3 Access Protection

0 (00): No access may be performed by this master

1 (01): Only read accesses may be performed by this master

2 (10): Only write accesses may be performed by this master

3 (11): Both read and write accesses may be performed by this master
M4AP

Master 4 Access Protection

0 (00): No access may be performed by this master

1 (01): Only read accesses may be performed by this master

2 (10): Only write accesses may be performed by this master

3 (11): Both read and write accesses may be performed by this master
M5AP

Master 5 Access Protection

0 (00): No access may be performed by this master

1 (01): Only read accesses may be performed by this master

2 (10): Only write accesses may be performed by this master

3 (11): Both read and write accesses may be performed by this master
M6AP

Master 6 Access Protection

0 (00): No access may be performed by this master

1 (01): Only read accesses may be performed by this master

2 (10): Only write accesses may be performed by this master

3 (11): Both read and write accesses may be performed by this master
M7AP

Master 7 Access Protection

0 (00): No access may be performed by this master.

1 (01): Only read accesses may be performed by this master.

2 (10): Only write accesses may be performed by this master.

3 (11): Both read and write accesses may be performed by this master.
M0PFD

Master 0 Prefetch Disable

0 (0): Prefetching for this master is enabled.

1 (1): Prefetching for this master is disabled.
M1PFD

Master 1 Prefetch Disable

0 (0): Prefetching for this master is enabled.

1 (1): Prefetching for this master is disabled.
M2PFD

Master 2 Prefetch Disable

0 (0): Prefetching for this master is enabled.

1 (1): Prefetching for this master is disabled.
M3PFD

Master 3 Prefetch Disable

0 (0): Prefetching for this master is enabled.

1 (1): Prefetching for this master is disabled.
M4PFD

Master 4 Prefetch Disable

0 (0): Prefetching for this master is enabled.

1 (1): Prefetching for this master is disabled.
M5PFD

Master 5 Prefetch Disable

0 (0): Prefetching for this master is enabled.

1 (1): Prefetching for this master is disabled.
M6PFD

Master 6 Prefetch Disable

0 (0): Prefetching for this master is enabled.

1 (1): Prefetching for this master is disabled.
M7PFD

Master 7 Prefetch Disable

0 (0): Prefetching for this master is enabled.

1 (1): Prefetching for this master is disabled.

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data